1. Field of the Invention
This invention relates to nonvolatile semiconductor memory devices and write or programming processes for nonvolatile semiconductor memory devices.
2. Description of Related Art
EEPROMs, unlike many other nonvolatile memories, can electrically erase old data and write new data. This flexibility in data management makes EEPROMs the preferred nonvolatile memory in system programming, where data may be refreshed and must be available when a system powers up.
A conventional memory cell in an EEPROM includes an N-channel cell transistor, which has a floating gate over a channel region defined between N+ source and drain in a P-type substrate, and a control gate overlying the floating gate. The floating and control gates are made out of a conductive material such as polysilicon, a silicide, or a metal, and insulation layers are between the control and floating gates, and between the floating gate and the channel region.
In flash EEPROM, a common mechanism for erasing and programming memory cells is Fowler-Nordhiem (F-N) tunneling. F-N tunneling changes the threshold voltage of a cell transistor by changing the amount of charge trapped on the floating gate of the cell transistor. For example, an exemplary erase operation applies a high voltage to a substrate while applying a low or negative voltage to the control gate of an N-channel cell transistor. The floating gate, which is between the control gate and the substrate, has a voltage that depends on the net charge trapped on the floating gate, the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate. If the voltage difference between the floating gate and the substrate is larger than a voltage gap required for the F-N tunneling, electrons held in the floating gate tunnel from the floating gate into the substrate. The tunneling of the electrons from the floating gate to the substrate lowers the threshold voltage Vt of the cell transistor.
When the threshold voltage Vt is sufficiently low, the cell transistor conducts a channel current when 0V is applied to the control gate and source of the cell transistor and a positive voltage is applied to drain of the cell transistor. A cell transistor having this lowered threshold voltage is referred to as an xe2x80x9cerased cellxe2x80x9d or as being in an xe2x80x9cerased state,xe2x80x9d which represents data value xe2x80x9c1xe2x80x9d.
In an exemplary programming operation that writes a data value xe2x80x9c0xe2x80x9d into a cell transistor, a low voltage (e.g., 0V) is applied to the source and drain of the cell transistor, and a high voltage (often more that 10V) is applied to the control gate of the cell transistor. In response, an inversion layer forms in a channel region under the floating gate. This channel region (i.e., the inversion layer) has the same voltage (0V) as the source and drain. When a voltage difference between the floating gate and the channel voltage becomes high enough to cause the F-N tunneling, electrons tunnel to the floating gate from the channel region, thereby increasing the threshold voltage of the cell transistor. A programming operation raises the threshold voltage of a cell transistor high enough to prevent channel current through the cell transistor when a positive read voltage is applied to the control gate, the source is grounded, and a positive voltage is applied to drain. A cell transistor having the raised threshold voltage is referred to as a xe2x80x9cprogrammed cellxe2x80x9d or as being in a xe2x80x9cprogrammed state,xe2x80x9d which represents data value xe2x80x9c0xe2x80x9d.
EEPROMs can also achieve the high integration densities necessary for an inexpensive non-volatile memory. In particular, flash EEPROMs achieve high integration density that is adaptable to large capacity subsidiary storage elements, and more specifically, NAND-type flash EEPROMs provide higher integration densities than do the other well-known types of EEPROM (e.g., NOR or AND type EEPROM).
A convention NAND-type EEPROM includes a cell array containing NAND strings, where each NAND string includes a set of cell transistors connected in series. FIG. 1 shows a conventional NAND-type flash EEPROM 100 including a cell array 110 containing multiple NAND strings 112. In cell array 110, each NAND string 112 includes a first select transistor ST, M+1 (e.g., 16) cell transistors M0 to MM, and a second select transistor GT connected in series. Each first selection transistor ST has a drain connected to a corresponding bit line. Generally, all NAND strings in a column of cell array 110 share the same bit line. The second selection transistor GT in each NAND has a source connected to a common source line CSL for the sector containing the NAND string. Gates of the first and second selection transistors in a row of NAND strings 112 are respectively coupled to a string selection line SSL and a ground selection line GSL corresponding to the row. Each word line in cell array 110 connects to the control gates of all cell transistors in a corresponding row of cell array 110.
NAND-type flash memory 100 further includes a page buffer including latch circuits 130, sense circuits (not shown), and a Y or column decoder (Y pass gates 140). The sense circuits sense the states of selected bit lines to generate output data during a read operation. Latch circuits 130 control the voltages of selected bit lines for a write operation as described further below. An X or row decoder (not shown) activates a string selection line to select a row of NAND strings 112 and a word line that is coupled to the control gates of the cell transistors to be accessed. For reasons described further below, switching transistors 126 and 122e or 122o connect either the even numbered bit lines or the odd numbered bit lines to the sense circuits or latch circuits 130. Y pass gates 140 control and select data input/output of sense and latch circuits.
In array 110, a page includes a set of the cell transistors coupled to a word line associated with the page, and a block or sector is a group of pages. A block can include one or more NAND strings 112 per bit line. Typically, a read or write operation simultaneously reads or programs and entire page of memory cells, and an erase operation erases an entire block or sector.
To program a selected memory cell M1 in NAND flash memory 100, a bit line BL0 assigned to the memory string 112 including a selected memory cell M1 is biased to 0V. The string selection line SSL for the NAND string 112 containing the selected memory cell M1 is biased to the supply voltage Vcc to turn on the first selection transistor ST, and the ground selection line GSL is biased to 0V to turn off the second selection transistor GT. The word line WL1 connected to the control gate of the selected memory cell M1 is biased to a high voltage. Capacitive coupling between the control gate and the floating gate raises the floating gate to a voltage near the high voltage. In response to the voltage difference between the channel region and the floating gate in the selected memory cell M1, electrons from the channel region tunnel into the floating gate of the selected memory cell, thereby increasing the threshold voltage of the selected memory cell M1 to a positive level.
All control gates of memory cells included in the selected page are at the high voltage for a write operation. However, the page typically includes memory cells that will be programmed to store bit value xe2x80x9c0xe2x80x9d and other memory cells to be left in the erased state (i.e., are not programmed) and represent data value xe2x80x9c1xe2x80x9d. To avoid programming a memory cell in the same page as memory cells being programmed, the channel voltage of the memory cell is boosted to reduce the voltage gap between the floating gate and the channel region. The lower voltage gap prevents significant F-N tunneling and keeps the memory cell in the erased state while other memory cells in the same page are programmed.
One useful technique for selectively increasing a channel voltage of a memory cell is often called xe2x80x9cself-boostingxe2x80x9d. During self-boosting, the capacitive coupling between the floating gate and the channel region increases the channel voltage of a memory cell as the word line and floating gate voltages increase. Additionally, a corresponding bit line (i.e., a bit line not connected to a cell being programmed) and string selection line SSL are at a power supply voltage Vcc. Word lines other than the selected word line are at a voltage Vpass that is in a range between the control gate voltage required to turn on a memory cell and a voltage high enough to cause programming. With this biasing, the string selection transistor, which has a gate at supply voltage Vcc, turns off when the channel voltage of a cell transistor in the corresponding string reaches a voltage Vcc-Vth where Vth is the threshold voltage of the string selection transistor. The channel voltage can further rise from the Vcc-Vth to higher levels along the word line at the programming voltage.
Before programming, a xe2x80x9cbit line setupxe2x80x9d pre-charges to 0V the bit lines for the selected memory cells to be programmed and pre-charges to supply voltage Vcc the bit lines not connected to a memory cell to be programmed. After programming, all of bit lines are discharged to 0V during a xe2x80x9cbit line dischargexe2x80x9d.
Recent NAND flash EEPROM chips use more dense design rules (e.g., closer line spacing) to achieve higher levels of integration. The increased density increases the coupling capacitance between adjacent conductive lines such as bit lines. The larger coupling capacitance between adjacent bit lines makes malfunctions more likely when adjacent bit lines are charged for writing different data values. In particular, a bit line at 0V can pull down the voltage of a neighboring bit line intended to be at supply voltage Vcc, and the write operation can disturb or program the threshold voltage of an cell transistor that was intended to remain erased.
One proposal for overcoming the problems associated with the bit line couplings is to have adjacent bit lines coupled to memory cells in different pages. Accordingly, in this architecture, which is said to employ xe2x80x9cshielded bit linesxe2x80x9d, sense amplifiers and latch circuits 130 are only available for half of the bit lines and page selection transistors 122e and 122o select a page (even or odd bit lines) for a read or programming operation. Reading or programming is still performed in the unit of a page, but an unselected bit line acts as a shield between adjacent bit lines that are in the selected page. Accordingly, the influence between selected bit lines is greatly reduced.
However, program inhibition in the shielded bit line architecture charges bit lines assigned to a non-selected page (hereinafter referred to as xe2x80x9cshielded bit linesxe2x80x9d) and bit lines connected to memory cell that are in a selected page but not to be programmed. A page buffer 135 can charge bit lines in the selected page to supply voltage Vcc or 0V according to corresponding data bits held in corresponding latch circuits 130. Charging the shielded bit lines up to supply voltage Vcc requires additional circuitry because page buffers 130 are required for the access of the selected page.
Memory 100 of FIG. 1 includes a conventional circuit that performs the bit line setup and discharging. As shown in FIG. 1, drains of MOSFETs 102e and 102o act as connecting circuits that connect respective even and odd bit lines to a virtual power node VIRPWR. Sources of the MOSFETs 150e and 150o connect in common to node VIRPWR, and an inverter 104 charges node VIRPWR to supply voltage Vcc during a bit line setup and to ground (0V) when all of the bit line discharge.
For bit line setup, inverter 104 charges node VIRPWR to supply voltage Vcc. Assuming that even-numbered bit lines are selected for programming, a signal VBLo is activated to turn on MOSFETs 102o and thereby charge the non-selected bit lines (i.e., odd-numbered bit lines) to supply voltage Vcc. (Gate selection signal VBLe remains deactivated during bit line setup if even-numbered bit lines are selected for programming.) After completing a programming operation, node VIRPWR goes to 0V, and signals VBLe and VBLo are both activated to turn on all MOSFETs 102o and 102e, thereby discharging all the bit lines to 0V.
As circuit density, data access rates, and required charging and discharging capacities increase, bit line setup and bit line discharge cause more noise in the power supply voltages Vcc or the ground voltage. In particular, the rapid switching when driving virtual power node VIRPWR to supply voltage Vcc or ground creates a large transient noise peak. Such noise concerns are likely to worsen as the memory circuit densities increase since the bit line setup raises half of the bit lines (the even-numbered or the odd-numbered) to supply voltage Vcc before programming. Further, discharging bit lines to ground (0V) in the worst case discharges all of bit lines after programming.
In accordance with the invention, disclosed circuits and methods reduce the power and ground noise that occur when charging bit lines up to supply voltage Vcc or discharging the bit lines to ground (0V). In particular, one embodiment of the invention is a NAND EEPROM having a shielded bit line architecture. This NAND EEPROM has a virtual power node that is connected to bit lines for charging or discharging of the bit lines. A PMOS pull-up transistor and an NMOS pull down transistor connect to the virtual power node, and a control circuit for charging or discharging bit lines controls the gate voltages of the PMOS pull-up transistor and the NMOS pull-down transistor to limit peak current when charging or discharging bit lines. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages.
One programming operation in accordance with the invention sets up bit lines by pre-charging unselected bit lines via the virtual power node and the PMOS pull-up transistor having controlled gate voltage. Latches in the programming circuitry of the EEPROM charge or discharge selected bit lines according to respective data bits being stored. At the end of the programming operation, all of the bit lines are discharged via the virtual power node and the NMOS pull-down transistor, which then has a controlled gate voltage.
Another bit line setup includes two stages. The first stage pre-charges all bit lines via the virtual power node and PMOS pull-up. The second stage uses the latches in a page buffer to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry that connect the page buffer to the bit lines can be controlled to reduce noise caused by discharging selected bit lines through the latches.
Yet another embodiment of the invention is a non-volatile memory device such as a NAND flash EEPROM having a shielded bit line architecture. The non-volatile memory device includes an array of memory cells and a bit line bias circuit. The array of memory cells includes bit lines coupled to memory cells in respective columns of the array and word lines coupled to the memory cells in respective rows of the array. The bias circuit is coupled to the bit lines and includes a switch and a control circuit. The control circuit operates the switch to limit peak current drawn when simultaneously changing the voltage on a set of the bit lines.
In one embodiment, the switch includes a first PMOS transistor coupled between a supply voltage and a virtual power node and/or a first NMOS transistor coupled between a ground and the virtual power node. A connecting circuit selectably connects the virtual power node to even and odd bit lines. In another embodiment, the bias circuit includes NMOS transistors that are between the bit lines and respective latches in a page buffer for the memory device.
The control circuit controls the gate voltage of the PMOS and/or NMOS transistors. In particular, the control circuit can bias a PMOS transistor to conduct less than a saturation current to control current when charging bit lines, turn on the PMOS transistor to maintain the charged state of the bit lines, and turn off the PMOS transistor for discharging of the bit lines. Similarly, the control circuit can bias an NMOS transistor to conduct less than a saturation current to control current when discharging bit lines, turn on the NMOS transistor to maintain the discharged state of the bit lines, and turn off the NMOS transistor for charging of the bit lines. Accordingly, the non-volatile memory device can limit current and reduce noise when a virtual power node is used to charge or discharge bit lines or when a page buffer discharges bit lines.
In one embodiment, the control circuit includes: an output terminal connected to the gate of the first PMOS transistor; sources of a reference voltage, the supply voltage, and a ground voltage; and a switch circuit operable to connect any of the reference voltage, the supply voltage, and the ground voltage to the output terminal. The source of the reference voltage can include a second PMOS transistor and a second NMOS transistor connected in series between the supply voltage and the ground voltage. A gate and a drain of the second PMOS transistor are connected together and provide the reference voltage, and when the switch circuit operates to connect the reference voltage to the output terminal, current through the first PMOS transistor mirrors a current through the second PMOS transistor.
Another exemplary embodiment of the invention is a nonvolatile memory including a cell array, a virtual power node and a connecting circuit. The connecting circuit controls connections of the virtual power node to bit lines in the cell array for charging or discharging of the bit lines then connected to the virtual power node. A PMOS transistor, an NMOS transistor, and a control circuit control the current flowing through the virtual power node. The PMOS transistor is coupled between the virtual power node and a supply voltage, and the NMOS transistor is coupled between the virtual power node and a ground. The control circuit applies a first control signal to a gate of the PMOS transistor and a second control signal to a gate of the NMOS transistor.
One embodiment of this control circuit includes a first switch coupled between a source of a first reference voltage and a first node for output of the first control signal. When the first switch is activated, the first control signal is at the first reference voltage, and the first reference voltage applied to the gate of the PMOS transistor causes the PMOS transistor to conduct a non-saturation current.
The control circuit typically further includes a second switch coupled between a source of a second reference voltage and a second node for output of the second control signal. When the second switch is activated, the second control signal is at the second reference voltage, and the second reference voltage applied to the gate of the NMOS transistor causes the NMOS transistor to conduct a non-saturation current.
The control circuit may further include first and second pairs of series-connected transistors. The first pair of transistors is connected in series between the supply voltage and ground, with the first node being between the transistors in the first pair. The second pair of transistors is connected in series between the supply voltage and ground, with the second node being between the transistors in the second pair. Turning on one of the transistors in either pair can set the first and second control signals at ground or the supply voltage to maintain the virtual power node as required for charging or discharging of bit lines.
This embodiment of the non-volatile memory may further include: a page buffer; a plurality of NMOS transistors coupled between the page buffer to the bit lines of the cell array; and a control circuit. The control circuit operates the NMOS transistors to conduct a non-saturation current when the page buffer discharges one or more of the bit lines.
Another embodiment of the invention is a programming method for a non-volatile memory. The programming method includes pre-charging bit lines to a first voltage by operating a switch that is between the first voltage and the bit lines and thereby limiting peak current flowing through the switch to the plurality of bit lines. Applying a second voltage to a selected word line programs one or more selected memory cells coupled to the selected word line, but the first voltage remaining on one of the bit lines prevents programming of a memory cell coupled to that bit line and the selected word line. Typically, the switch comprises a transistor and operating the switch comprises controlling the transistor to conduct less than a saturation current, for example, by connecting the transistor into a current mirror circuit that limits the current through the transistor.
The pre-charging can charge all bit lines or just the unselected bit lines. When just the unselected bit lines are charged, latches in a page buffer for the memory charge or discharge selected bit lines according to corresponding data bits to be written. When pre-charging charges all bit lines, the page buffer only needs to discharge or maintain the charged state of selected bit lines according to the data bits being written. When the only currents through the latches are discharging bit lines to ground, the gate voltages of NMOS transistors connecting the latches to the bit lines can control the current and reduce noise caused by current through the latches.
Yet another embodiment of the invention is programming method that includes: pre-charging selected bit lines and unselected bit lines to a first voltage using current through a PMOS transistor that has a gate voltage controlled to limit current flow to the selected and unselected bit lines. The unselected bit lines are interleaved among the selected bit lines. After pre-charging, the programming method further includes discharging at least some of the selected bit lines to corresponding data latches through a plurality of NMOS transistors that are between the selected bit lines and the data latches. Gate voltages of the NMOS transistors are controlled to limit current through the NMOS transistors during the discharging. Applying a second voltage to a selected word line programs one or more selected memory cells coupled to the selected word line, but the first voltage remaining on one of the bit lines prevents programming of a memory cell coupled to that bit line and the selected word line.